This patent portfolio generally relates to an architecture employed in advanced pipeline microprocessors. This architecture allows for conditional execution of microprocessor instructions, and a later determination of whether the instructions executed should be written back to memory. By conditionally executing instructions in this architecture, significant improvements in microprocessor speed can be achieved. Certain pipelined processor manufacturers are adopting this method of processing to improve processor speed. This portfolio also includes compiler optimization and hardware circuitry technologies for use in processor and memory designs.